1. Field of the Invention
The invention relates in general to a wafer structure, and more particularly to a wafer structure of enhancing the mechanical strength of the UBM layer.
2. Description of the Related Art
Along with the popularity of information technology, the application of multi-media product is gaining rapid growth. Meanwhile, the integrated circuit packaging technology has to take the current trends of digitalization, networkization, localization and personalization in electronic devices into consideration. In order to satisfy the above requirements, electronic elements must possess the features of high-speed processing, multi-functions, integration, miniaturization, light weight and low price. Therefore, the integrated circuit packaging technology is directed towards miniaturization and high density, and high density integrated circuit packaging technologies such as ball grid array (BGA), chip-scale package (CSP), flip chip (F/C), multi-chip module (MCM) are thus developed.
The integrated circuit packaging density refers to the number of pins per unit area. In terms of integrated circuit packaging, the length of wiring is shortened to improve the speed of signal transmission, and the application of bumps has become dominated high density packaging.
FIG. 1 is a cross-sectional view of a conventional flip-chip structure. In FIG. 1, the flip-chip package structure 100 includes a semiconductor substrate 110, a number of under bump metallurgy (UBM) layers 120, a number of bumps 130 and a chip 140. Only one of the UBM layers 120 and one of the bumps 130 are illustrated in FIG. 1. The semiconductor substrate 110 has an active surface 110a, a bonding pad 112 and a passivation layer 114. The bonding pad 112 is positioned on the active surface 110a of the semiconductor substrate 110. The passivation layer 114 covers the active surface 110a and exposes part of the bonding pad 112. The UBM layer 120 is disposed on bonding pads 112 and includes an adhesion layer 122, a barrier layer 124 and a wetting layer 126. The adhesion layer 122 is positioned on the bonding pad 112 of the semiconductor substrate 110. The barrier layer 124 is positioned on the adhesion layer 122. The wetting layer 126 is positioned on the barrier layer 124. The bump 130 is positioned on the wetting layer 126. The connecting pad 142 of chip 140 is electrically connected to the semiconductor substrate 110 via the bump 130.
It is noted that when the semiconductor substrate 110 and the chip 140 are heated, the coefficients of thermal expansion (CTE) of the two elements will dismatch, causing the bump 130 and the UBM layer 120 to receive horizontal shear force. The UBM layer 120 is very thin and has weak mechanical strength. Therefore, the UBM layer 120 will break when the shear force received by the UBM layer 120 is beyond the tolerable level, causing the electric connection between the semiconductor substrate 110 and the chip 140 to be disconnected, deteriorating the reliability of the flip-chip package structure 100.